? semiconductor components industries, llc, 2006 november, 2006 ? rev. 5 1 publication order number: nb2305a/d nb2305a 3.3 v zero delay clock buffer the nb2305a is a versatile, 3.3 v zero delay buffer designed to distribute high ? speed clocks. it accepts one reference input and drives out five low ? skew clocks. it is available in a 8 pin package. the ? 1h version of the nb2305a operates at up to 133 mhz, and has higher drive than the ? 1 devices. all parts have on ? chip pll?s that lock to an input clock on the ref pin. the pll feedback is on ? chip and is obtained from the clkout pad. multiple nb2305a devices can accept the same input clock and distribute it. in this case the skew between the outputs of the two devices is guaranteed to be less than 700 ps. all outputs have less than 200 ps of cycle ? to ? cycle jitter. the input and output propagation delay is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250 ps. the nb2305a is available in two different configurations, as shown in the ordering information table. the nb2305a1 is the base part. the nb2305ax1h* is the high drive version of the ? 1 and its rise and fall times are much faster than ? 1 part. features ? 15 mhz to 133 mhz operating range, compatible with cpu and pci bus frequencies ? zero input ? output propagation delay ? multiple low ? skew outputs ? output ? output skew less than 250 ps ? device ? device skew less than 700 ps ? one input drives 5 outputs ? less than 200 ps cycle ? to ? cycle jitter is compatible with pentium based systems ? available in 8 pin, 150 mil soic package and 8 pin tssop 4.4 mm ? 3.3 v operation, advanced 0.35 cmos technology ? these are pb ? free devices *x = c for commercial; i for industrial. marking diagrams* xxxx = device code a = assembly location l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) *for additional marking information, refer to application note and8002/d. 1 8 soic ? 8 d suffix case 751 see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information http://onsemi.com 1 8 tssop ? 8 dt suffix case 948j xxxx alyw 1 8 xxx alyw 1 8
nb2305a http://onsemi.com 2 figure 1. block diagram ref pll clkout clk1 clk2 clk3 clk4 figure 2. pin configuration v dd 1 2 3 4 8 7 6 5 ref clk2 clk1 gnd clkout clk4 clk3 nb2305a table 1. pin description pin # pin name description 1 ref (note1) input reference frequency, 5 v tolerant input. 2 clk2 (note 2) buffered clock output. 3 clk1 (note 2) buffered clock output. 4 gnd ground. 5 clk3 (note 2) buffered clock output. 6 v dd 3.3 v supply. 7 clk4 (note 2) buffered clock output. 8 clkout (note 2) buffered clock output, internal feedback on this pin. 1. weak pulldown. 2. weak pulldown on all outputs.
nb2305a http://onsemi.com 3 table 2. maximum ratings parameter min max unit supply voltage to ground potential ? 0.5 +7.0 v dc input voltage (except ref) ? 0.5 v dd + 0.5 v dc input voltage (ref) ? 0.5 7 v storage temperature ? 65 +150 c maximum soldering temperature (10 sec) 260 c junction temperature 150 c static discharge voltage (per mil ? std ? 883, method 3015) >2000 v maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. table 3. operating conditions for commercial and industrial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) commercial industrial 0 ? 40 70 85 c c l load capacitance, below 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 10 pf c in input capacitance 7 pf table 4. electrical characteristics for commercial and industrial temperature devices parameter description test conditions min max unit v il input low voltage (note 3) 0.8 v v ih input high voltage (note 3) 2.0 v i il input low current v in = 0 v 50 a i ih input high current v in = v dd 100 a v ol output low voltage i ol = 8 ma ( ? 1) i ol = 12 ma ( ? 1h) 0.4 v v oh output high voltage i oh = ? 8 ma ( ? 1) i oh = ? 12 ma ( ? 1h) 2.4 v i dd supply current (commercial temp) unloaded outputs at 66.67 mhz, select inputs at v dd 34 ma i dd supply current (industrial temp) unloaded outputs at 100 mhz 66.67 mhz 33 mhz select inputs at v dd or gnd, at room temp 50 34 19 ma 3. ref input has a threshold voltage of v dd /2.
nb2305a http://onsemi.com 4 table 5. switching characteristics (commercial and industrial) (note 4) parameter description test conditions min typ max unit 1/t 1 output frequency 30 pf load 10 pf load 15 15 100 133.33 mhz 1/t 1 duty cycle = (t 2 / t 1 ) * 100 ( ? 1, ? 1h) ( ? 1h) measured at 1.4 v, f out = 66.67 mhz < 50 mhz 40 45 50 50 60 55 % t 3 output rise time ( ? 1) ( ? 1h) measured between 0.8 v and 2.0 v 2.5 1.5 ns t 4 output fall time ( ? 1) ( ? 1h) measured between 2.0 v and 0.8 v 2.5 1.5 ns t 5 output ? to ? output skew all outputs equally loaded 250 ps t 6 delay, ref rising edge to clkout rising edge measured at v dd /2 0 350 ps t 7 device ? to ? device skew measured at v dd /2 on the clkout pins of the device 0 700 ps t j cycle ? to ? cycle jitter measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time stable power supply, valid clock presented on ref pin 1.0 ms tr in ref input rise time measured between 0.8 v to 2.0 v 1.0 ns tf in ref input rise fall time measured between 2.0 v to 0.8 v 1.0 ns 4. all parameters specified with loaded outputs.
nb2305a http://onsemi.com 5 zero delay and skew control all outputs should be uniformly loaded to achieve zero delay between input and output. since the clkout pin is the internal feedback to the pll, its relative loading can adjust the input ? output delay. for applications requiring zero input ? output delay, all outputs, including clkout, must be equally loaded. even if clkout is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero ? input ? output delay. switching waveforms figure 3. duty cycle timing 1.4 v 1.4 v 1.4 v t 1 t 2 figure 4. all outputs rise/fall time t 3 output 2.0 v 0.8 v t 4 2.0 v 0.8 v 3.3 v 0 v 1.4 v 1.4 v t 5 figure 5. output ? output skew output output t 6 input output figure 6. input ? output propagation delay v dd 2 v dd 2 figure 7. device ? device skew t 7 clkout, device 1 v dd 2 v dd 2 clkout, device 2
nb2305a http://onsemi.com 6 test circuits v dd v dd c load gnd gnd outputs figure 8. test circuit #1 10 pf 0.1 f 0.1 f v dd v dd gnd gnd outputs 0.1 f 0.1 f 1 k 1 k figure 9. test circuit #2 for parameter t 8 (output slew rate) on ? 1h devices v dd clkout ordering information device marking operating range package shipping ? availability nb2305ac1dg 5c1 commercial soic ? 8 (pb ? free) 98 units / rail now nb2305ac1dr2g 5c1 commercial soic ? 8 (pb ? free) 2500 tape & reel now nb2305ai1dg 5i1 industrial soic ? 8 (pb ? free) 98 units / rail now nb2305ai1dr2g 5i1 industrial soic ? 8 (pb ? free) 2500 tape & reel now NB2305AC1HDG 5c1h commercial soic ? 8 (pb ? free) 98 units / rail now nb2305ac1hdr2g 5c1h commercial soic ? 8 (pb ? free) 2500 tape & reel now nb2305ai1hdg 5i1h industrial soic ? 8 (pb ? free) 98 units / rail now nb2305ai1hdr2g 5i1h industrial soic ? 8 (pb ? free) 2500 tape & reel now nb2305ac1dtg 5c1 commercial tssop ? 8 (pb ? free) 100 units / rail now nb2305ac1dtr2g 5c1 commercial tssop ? 8 (pb ? free) 2500 tape & reel now nb2305ai1dtg 5i1 industrial tssop ? 8 (pb ? free) 100 units / rail now nb2305ai1dtr2g 5i1 industrial tssop ? 8 (pb ? free) 2500 tape & reel now nb2305ac1hdtg 5c1h commercial tssop ? 8 (pb ? free) 100 units / rail now nb2305ac1hdtr2g 5c1h commercial tssop ? 8 (pb ? free) 2500 tape & reel now nb2305ai1hdtg 5i1h industrial tssop ? 8 (pb ? free) 100 units / rail now nb2305ai1hdtr2g 5i1h industrial tssop ? 8 (pb ? free) 2500 tape & reel now ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb2305a http://onsemi.com 7 package dimensions soic ? 8 nb case 751 ? 07 issue ag 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m
nb2305a http://onsemi.com 8 package dimensions tssop ? 8 case 948j ? 01 issue a ??? ??? ??? dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n ? n seating plane ident. pin 1 1 4 8 5 see detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 8x ref k n n on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb2305a/d pentium is a registered trademark of intel corporation. licensed under us patent nos 5,488,627, 6,646,463 and 5,631,920. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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